1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and, more particularly, to the implanting of ions of dopant materials into workpieces and/or substrates suitable for the fabrication of integrated circuits. More specifically, the present invention relates to a method of amorphizing a crystalline substrate on which integrated circuits are fabricated.
2. Description of the Related Art
In the last several years, the numbers of circuit elements manufactured on semiconductor substrates has continuously grown, and the size of the circuit elements has continuously decreased accordingly. Presently, circuit elements are commonly fabricated featuring minimum sizes less than 0.18 μm and the progress in the manufacturing technology seems likely to continue to proceed in this manner.
However, in the case of field effect transistors, as process technology improved to the point where devices could be fabricated with a gate length less than 2 μm, the need arose to restrict the doping profiles of the several implants carried out during the manufacturing process to shallow locations. That is, implantations need to be confined within shallow well predefined regions. To obtain the shallow doping profiles required for, e.g., halo structures, source/drain regions and channels, all physical mechanisms allowing dopants to penetrate into the substrate must be strictly controlled or eliminated. In particular, the principal factor to be controlled is ion channeling.
To accomplish this end, great efforts have been made and several measures have been taken in the art. Among these measures, common manufacturing processes often use a so-called “pre-amorphization” implantation step before carrying out the usual dopant implantation steps. In particular, an amorphous zone is usually formed during a first pre-amorphization implantation and, during subsequent implantation processes, the doped regions (halo and source/drain extension regions) are formed. Normally, heavy inert ions like germanium or xenon are implanted at an implant energy of approximately 80-200 keV to fully amorphize the surface regions of the substrate.
In the following, a description will be given with reference to FIGS. 1a-1d of a typical prior art process for forming the active regions of a field effect transistor, including a typical “pre-amorphization” implanting step, as well as a typical “halo” implanting step and the implanting steps for forming the source and drain regions.
FIG. 1a schematically shows a MOS transistor 100 to be formed on a substrate 1, such as a silicon wafer. Isolation structures 2 define an active region of the transistor 100. Moreover, reference 3 relates to a polysilicon gate electrode of the MOS transistor 100. Reference 6 denotes a gate insulation layer. Reference 7a relates to an ion beam to which the substrate 1 is exposed during a “pre-amorphization” implanting process, and reference 5a relates to amorphous regions formed into the substrate 1.
In FIGS. 1b-1d, those parts already described with reference to FIG. 1a are identified by the same reference numerals. In addition, in FIG. 1b, reference 7h relates to an ion beam to which the substrate 1 is exposed for forming the halo regions 5h. The dopant material implanted during such a process is of the same type as the dopant used for doping the substrate. That is, the halo implants for NMOS and PMOS devices are performed using a P-type and an N-type dopant material, respectively. In a sense, the halo implants reinforce the dopants in the substrate.
In FIG. 1c, reference 7e relates to an ion beam to which the substrate 1 is exposed for forming the source/drain extension regions of the transistor 100. Moreover, references 5′S and 5′D relate to the source extension region and the drain extension region, respectively, of the transistor 100. Still, in FIG. 1c, reference e relates to a portion of the transistor 100 which is depicted in enlarged view in FIG. 1c′, in which corresponding reference numerals identify corresponding parts already described with reference to FIG. 1c. 
In FIG. 1d, reference 4 relates to dielectric sidewall spacers formed on the sidewalls of the polysilicon line 3 and references 5S and 5D relate to the source and drain regions, respectively, after a further heavy implantation step has been carried out for determining the final concentration of dopants in the source and drain regions. Finally, in FIG. 1d, reference 7SD identifies an ion beam to which the substrate 1 is exposed for forming the source and drain regions 5S and 5D.
A typical process flow for forming the active regions of the transistor 100 comprising the amorphous regions 5a, the halo structures 5h and the source and drain regions 5S and 5D may include the following steps.
Following the formation of the gate insulation layer 6 and the overlying polysilicon line 3 according to well-known lithography and etching techniques, the amorphous regions 5a are formed during a first pre-amorphization implantation step (see FIG. 1a). To this end, the substrate 1 is exposed to the ion beam 7a and heavy ions, such as phosphorous, arsenic and argon are implanted into the substrate at an implanting energy of about 80 keV. The ion beam 7a is normally kept perpendicular or at a weak tilt angle (up to 10 degrees) with respect to a direction perpendicular to the surface of the substrate 1.
It has been observed that at a predefined implanting dose, local amorphous regions are created by the ions penetrating into the substrate, which eventually overlap until a continuous amorphous layer is formed. This amorphous layer (or the amorphous regions 5a) is formed with the purpose of controlling ion channeling during the next implanting steps so as to obtain shallow implanting profiles for both the halo regions and the source and drain regions to be formed in a substrate. That is, the implanted ions do not penetrate in an amorphous layer as deeply as in a crystalline layer so that the implanted ions can be confined to shallower regions and the actual doping profile and final dopant concentration of those regions implanted after the pre-amorphization implantation step can be better controlled. However, due to the fact that the amorphous regions 5a are formed with a non- or weakly-tilted implantation beam, only the vertical penetration depth of subsequent doping profiles can be reduced.
In a next step, as depicted in FIG. 1b, the halo regions 5h of the transistor 100 are formed. In particular, a further ion implantation step is carried out during which the substrate is exposed to an ion beam 7h. As depicted in FIG. 1b, during the depicted halo implant, the ion beam 7h is kept perpendicular with respect to the surface of the substrate 1 or the ion beam 7h is weakly tilted (up to 10 degrees) with respect to a direction perpendicular to the surface of the substrate 1. The dopant concentration in the regions 5h, as well as the implant energy of the dopants, are selected depending on the type of transistor to be formed on the substrate 1. For instance, boron ions in NMOS and phosphorous ions in PMOS are implanted to form a halo punch-through suppression region in each device. Usually, boron is implanted at 90 keV with a dose of 2×1013 cm−2. Similar procedures are used for implanting phosphorous. A thermal treatment, such as an annealing step, is usually performed after the ion implantation step for diffusing dopants into the substrate.
As is apparent from FIG. 1d, the halo regions 5h, in correspondence with the edges of the polysilicon line 3 and the gate 6, extend outside the amorphous zones 5a. This is due to the fact that, during the implantation steps for forming the amorphous zones 5a, the ion beam is kept substantially perpendicular with respect to the surface of the substrate 1, so that the edges of these amorphous regions 5a are substantially aligned with the edges of the gate 6. Accordingly, ion channeling during the subsequent implantation steps for forming the halo structures 5h cannot be adequately controlled in the horizontal direction or, in other words, the doping profile of the halo regions 5h cannot be kept as shallow as desired in the horizontal direction but portions of the halo regions are formed extending beyond the amorphous regions 5a. 
During a next step, as depicted in FIG. 1c, a third ion implantation step is carried out to form the source/drain extension regions 5′S and 5′D. To this end, by exposing the substrate 1 to an ion beam 7e, a dose of approximately 3×1013-3×1014 cm−2 dopant ions is implanted at low energy (3 to 5 keV). This third ion implantation step is performed with N-type and P-type dopant materials for NMOS and PMOS devices, respectively. The problem arising during the halo implantation step of FIG. 1b, namely that ion channeling cannot be adequately controlled in the horizontal direction, arises during the ion implantation step of FIG. 1c as well. Accordingly, the source and drain regions 5′S and 5′D cannot be contained inside the amorphous regions 5a previously formed, but portions of the source and drain regions 5′S and 5′D extend beneath the layer 6 and the overlying polysilicon line 3, especially after a heat treatment process is performed. Accordingly, the doping profiles of the source and drain regions 5′S and 5′D cannot be kept as shallow as desired in the horizontal direction.
In particular, the situation after the implanting step of FIG. 1c is that depicted in enlarged view in FIG. 1c′, with the doping profiles of both the source and drain extension regions 5′S and the halo regions 5h extending beyond the doping profile of the amorphous regions 5a, in correspondence with the edges of the layer 6 and the overlying polysilicon line 3.
During a subsequent step, the source and drain regions 5S and 5D of the transistor 100 are completed, as depicted in FIG. 1d. In particular, dielectric sidewalls spacers 4 are formed on the sidewalls of the polysilicon line 3 according to well-known techniques and a further heavy implantation step is carried out for implanting dopants into those regions of the substrate not covered by the polysilicon line 3 and the sidewall spacers 4. At the end of the heavy implantation step, the source and drain regions 5S and 5D are formed to exhibit the desired dopant concentration. For NMOS and PMOS type devices, this heavy implantation step is performed using an N-type and P-type dopant material, respectively. The manufacturing process is then continued to complete the transistor 100 according to techniques well known to those skilled in the art.
As stated above, the pre-amorphization implanting process as depicted in FIG. 1a is performed for the purpose of controlling the ion channeling during the subsequent implanting steps to obtain doping profiles for both the halo structures and the source and drain regions that are as shallow as required in view of the reduced planar dimensions of modern transistors. That is, by pre-amorphizing the substrate, the dopants implanted into the substrate during subsequent implanting processes are confined to shallow regions of a reduced depth close to the surface of the substrate.
However, as stated above, the prior art pre-amorphization process as depicted with reference to FIG. 1a has the disadvantage that the ion channeling during subsequent implanting processes cannot be adequately controlled in the horizontal direction. Accordingly, the dopants implanted into the substrate during subsequent implanting processes may not be confined into shallow regions of predefined horizontal dimensions and the dopant concentration cannot be adequately controlled in correspondence with the channel edges. This, in particular, leads to reduced effective channel dimensions, with corresponding short channel effects, affecting the transistor.
Accordingly, in view of the problems explained above, it would be desirable to provide a technique that may solve or at least reduce one or more of these problems. In particular, it would be desirable to provide a technique that allows the prevention and/or reduction of ion channeling during halo implantation and source and drain implantation processes in both the vertical and the horizontal direction.